The performance of a high bandwidth analog-to-digital converter is often limited by the performance of the high frequency sampling clock that may be used. Such a high frequency sampling clock is typically generated from PLLs that suffer from jitter or phase noise impurities. The sampling clock jitter impurities may be induced into an output signal of the analog-to-digital converter and, therefore, deteriorate the performance of high end measurement instrumentation of an automated test equipment (ATE).